Combined placement and routing
Generates complete PCB layout candidates, addressing component placement and net routing as one problem. Quilter exposes the physics checks it runs so engineers can inspect the results.
Physics-driven AI for hardware teams automating PCB placement and routing.
Quilter automates printed circuit board (PCB) placement and routing using AI trained on synthetic boards and fundamental physics. It considers placement and routing together, checking layouts against the circuit’s electrical behavior.
Engineers prepare a schematic, board outline, and constraints in their ECAD tool, upload the project, and review generated candidates and physics checks. They can adjust the results and resubmit. Candidates still need engineering cleanup, design-rule checks, and manufacturing review before fabrication.
Generates complete PCB layout candidates, addressing component placement and net routing as one problem. Quilter exposes the physics checks it runs so engineers can inspect the results.
Routes around work completed before upload, including RF nets, high-voltage sections, and fan-outs. Already routed pins are excluded from the design pin count used for pricing.
Runs multiple versions of a board simultaneously, allowing comparisons of layer stack-ups, room configurations, and trace widths within the same project.
Returns standard board files for Altium, Cadence Allegro, Siemens Xpedition, and KiCad. Customers own the output and can modify or fabricate it.
The project offering includes first-board engineering guidance through file submission, the circuit comprehension report, and floor-plan setup, followed by check-ins during iteration.
Use a managed AWS cloud workspace or customer-hosted deployment. The enterprise version does not use customer data for training; the free version may use uploaded designs to generate synthetic training data. Choose the appropriate version before submitting confidential work.
Hardware teams can submit several boards in parallel to increase layout capacity when available design staff are already occupied.
Engineers can generate four-layer and six-layer candidates for the same design, then compare results before choosing a stack-up.
Designers can manually route sensitive circuit sections first, then submit the remaining placement and routing work to Quilter.
Organizations with data residency or network isolation requirements can deploy Quilter in their own Kubernetes environment, including fully air-gapped installations.
A free version provides PCB layout functionality, but uploads may be used to improve the model. Paid projects are priced by unrouted pins and include iterations within the same project. Changing the BOM by more than 10% creates a new project. Self-hosting has higher costs and may add fees.
Quilter is best suited to low-voltage, low-current designs with low-to-medium pin density. RF-dominant, high-voltage, and very high-density HDI designs are not a fit yet. For more complex boards, engineers can pre-route critical sections and evaluate whether the remaining work suits the tool.
Self-hosting uses a Helm chart in an existing Kubernetes cluster, with NVIDIA GPU resources for design jobs. Your infrastructure handles scheduling and scaling, and authentication integrates with your identity provider. Air-gapped operation is available when required.
Os dados de tráfego são apenas para referência.